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1 of 28 rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com product description features optimum technology matching? applied si bjt si bi-cmos gainp/hbt gaas hbt sige hbt gan hemt gaas mesfet si cmos sige bi-cmos ordering information lna 90 0 adc pll synthesizer driver 90 0 power control rf_i/o gfsk modem dac adc dac bluetooth link controller arm7tdmi? processor data sram firmware rom uart multi function i/os audio codec interface vtune chg_pump vbatt_ana vbatt_dig vcc_out vbb_out vdd_p address bus data bus cs, oe and we pll control voltage regulators and power distribution optional flash interface clk_req_out clk_req_in xtal_p/clk xtal_n clock distribution internal 50-ohm match network aux adc block diagram SIW3500 ultimateblue? the ultimateblue SIW3500? is a rf system on chip (soc) that combines a 2.4 ghz transceiver, baseband processor, and protocol stack software for bluetooth? wireless technology. due to its low power cmos process, the SIW3500 is ideally suited for applications such as mobile phones, audio headsets, and other embedded products. the SIW3500 integrates an arm7tdmi processor for software execution from either internal rom or external flash memory. the standard SIW3500 rom contains the bluetooth lower layer stack software including the hci transport driver. the SIW3500 is packaged in a 6 x 6 pb-free 96-vfbga that meets rohs (green) requirements. known good die (kgd) is available for special applications. rf system on chip (soc) for bluetooth wireless technology combining a 2.4 ghz transceiver, baseband processor, and protocol stack rom. bluetooth specificat ion v1.2 qualified including mandatory and optional functions such as afh and esco. manufactured using standard 0.18-micron cmos process technology. uart based host control interface (hci) transport layer supports standard and 3-wire modes. direct conversion rf architecture improves receiver-blocking performance. i/o voltage supply can range from 1.62 v to 3.63 v. -85 dbm receiver sensitivity and +2 dbm transmitter power typical performance specifications. integrated analog and digital voltage regulators simplify system design. 50 ? rf i/o does not need any additional external impedance matching components. flexible reference clock source options including cr ystal or direct input from the host platform. internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40 to +85c. on-chip rom software storage with patch capability. applications mobile phones and smart phones. bluetooth audio headset. bluetooth hands-free kit. SIW3500 ultimateblue? 0 60 0066 r00irf SIW3500 radio processor ds 9 preliminary december 13, 2004
preliminary 2 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds radio features rf system on chip (soc) for bluetooth wireless technology combining a 2.4 ghz transceiver, baseband processor, and protocol stack rom. bluetooth specification v1.2 qualified including mandatory and optional functions such as afh and esco. manufactured using standard 0.18 m cmos process technology. uart based host control interface (hci) transport layer supports standard and 3-wire modes. direct conversion rf architecture improves receiver-blocking performance. i/o voltage supply can range from 1.62 v to 3.63 v. -85 dbm receiver sensitivity and +2 dbm transmitter power typical performance specifications. integrated analog and digital voltage regulators simplify system design. 50 ? rf i/o does not need any additional external impedance matching components. flexible reference clock source options including crystal or direct input from the host platform. internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40 to +85c. on-chip rom software storage with patch capability. baseband features hardware based gfsk modem and packet processing contributes to lower system current consumption with minimal software overhead. arm7tdmi processor efficiently executes all protocol stack and application software. software execution from either internal rom or external flash memory. the SIW3500 features a rom patch mechanism that allows substituting small portions of rom code with code either downloaded from the host or stored in external eeprom. extensive multi function i/os allow flexible product configurations. auxiliary analog-to-digital converter (adc) is available for applications such as battery level detection. standard protocol stack features full-featured lower layer bluetooth protocol stack software up to the host interface (hci). bluetooth 1.2 qualified including mandatory and optional features such as afh, extended sco, faster connections, and lmp improvements. full bluetooth connection capabilities with support for piconet and scatternet modes and device scanning during sco connection. able to establish up to 3 sco connections simultaneously. supports low power connection states such as hold, sniff, and park modes with selectable sniff intervals. full support of bluetooth test modes for use during production. verified hci command level compatibility with multiple upper layer stack software. additional protocol stack features proprietary channel assessment algorithm provides fast and accurate determination of occupied channel for use in afh mode. in addition to afh, ultimateblue coexistence technology is part of the baseline protocol stack. ultimateblue coexistence minimizes interference to 802.11b/g products. the channel quality driven data rate (cqddr) feature optimizes data transfer in noisy or weak signal environments. full selection of upper layer protocol stack software and profiles available for license and customization.
preliminary 3 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds > = included in SIW3500 rom external system interfaces host hci transport (uart) the high speed uart interface provides the physical transport between the SIW3500 and the application host for the transfer of bluetooth data compliant with the bluetooth specification. the table below shows the supported configura- tions. the default baud rate is 115,200 bps and can be set depending on the product. host hci transport (3-wire uart) to reduce the number of signals and to increase the reliability of the hci uart interface, a 3-wire uart protocol is available in the SIW3500. the protocol is compliant with the bluetooth specification h:5 transport and backwards compatible with the bcsp 3-wire uart protocol. selection between h:4 uart, h:5 uart, and bcsp uart is done automatically by the SIW3500. audio codec interface the SIW3500 supports direct interface to an external audio codec or pcm host device. the interface provides the following configurations: standard pcm clock rates from 64 khz to 2.048 mhz with multi-slot handshakes and synchronization. supports either master or slave mode. supports any pcm data size up to 16 bits. compatible with motorola ssi mode. configuration of the codec interface is done by the firmware during boot-up using non-volatile memory (nvm) parameters. rom features SIW3500 hci SIW3500 headset protocol stack lower stack up to hci >> ultimateblue coexistence >> upper stack (l2cap, sdp, rfcomm) ? > programming interface (api) ? > profiles headset profile (hsp) ? > hands free profile (hfp) ? > SIW3500 radio processor hci uart parameters required host setting number of data bits 8 parity bit no parity stop bit 1 stop bit flow control rts/cts host flow-off response require ment from the SIW3500 8 bytes SIW3500 ic flow-off response requirement from host 2 bytes supported baud rates (bps) 9.6k, 19.2k, 38.4k, 57.6k, 115.2 k, 230.4k, 460.8k, 500k, 921.6k, 1m, 1.5m, 2m SIW3500 radio processor hci 3-wire uart parameters required host setting number of data bits 8 parity bit even stop bit 1 stop bit error detection slip and checksum sleep modes shallow and deep
preliminary 4 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds multi-function i/os (mfps) up to 8 (eight) multi-function i/o ports are available in the SIW3500. the table below identifies the i/os and their usage. external memory interface the SIW3500 does not require additional memory for standard below hci protocol functions. an external memory interface is available for execution of protocol stack software from flash memory if desired. if external flash memory will be used, the read access time of the device must be 100 ns or less. auxiliary uart the SIW3500 can be configured and enabled with an auxiliary uart port. this uart port can be used for debug depending on the application software. external power amplifier interface the SIW3500 supports the use of an external power amplifier for +20 dbm designs. when enabled, these signals provide an integrated interface for the control of an external pa. power management the host_wakeup and ext_wake signals are used for power management control of the SIW3500. host_wakeup is an output signal used to indicate bluetooth activity to the host. ext_wake is an input signal used by the host to wake up the SIW3500 from sleep mode. for control of the reference clock source, clock_req_in and clock_req_out can be made available to turn on/off an external reference clock source. general-purpose analog to digital converter (adc) the SIW3500 incorporates a general-purpose adc that can be enabled to sample external analog voltage. the adc has an 8-bit resolution. external eeprom controller and interface this interface is intended for communication to an optional eeprom when using the SIW3500 in rom mode. the eeprom is not required for configurations with external flash. the eeprom is the non-volatile memory (nvm) in the system and contains the system configuration parameters such as the bluetooth device address, the codec type, as multi function i/o number possible usage configuration mfp[0] general purpose. mfp[1] clock_req_in, host_wakeup, general purpose. mfp[2] address a[18], sync_clock, aux_rts, general purpose. mfp[3] freq_sel[3], sync_data, general purpose. mfp[4] freq_sel[1], general purpose. mfp[5] freq_sel[2], general purpose. mfp[6] aux_rxd, general purpose. mfp[7] aux_cts, tx_rx_switch, general purpose. signal description aux_txd tx data aux_rxd rx data aux_cts clear to send aux_rts request to send signal description idac power control to external pa. this output provides a variable current source that can be used to control the external pa. leave unconnected if not used tx_rx_switch output signal used to indica te the state of the radio. this could be used as a direction control for the pa. the polarity is programmable with the default set as: low = transmit; high = receive.
preliminary 5 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds well as other parameters. these default parameters are set at the factory, and some parameters will change depending on the system configuration. optionally, the memory parameters can be downloaded from the host processor at boot up eliminating the need for eeprom. please consult the application support team for details. the eeproms should have a serial i 2 c interface with a minimum size of 2 kbits and 16-byte page write buffer capabilities. general system requirements system reference clock the SIW3500 chip can use either an external crystal or a reference clock as the system clock input. a partial list of supported frequencies (in mhz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48. for other frequencies, please contact applications support. the system reference crystal/clock must have an accuracy of 20 ppm or better to meet the bluetooth specification. low power clock for the bluetooth low power clock, a 32.768 khz crystal can be used to drive the SIW3500 oscillator circuit, or alterna- tively, a 32.768 khz reference clock signal can be used instead of a crystal. if the lowest power consumption is not required during low-power modes such as sniff, hold, park, and idle modes, the 32.768 khz crystal may be omitted in the design. if the 32.768 khz clock source is used, the clock source should be connected to the clk32_in pin and must meet the following requirements: for ac-coupled via 100 pf or greater (peak-to-peak voltage): 400 mv p-p < clk32_in < v dd_c for dc-coupled: clk32_in minimum peak voltage < v il clk32_in maximum peak voltage > v ih where v il = 0.3 * v dd_c where v ih = 0.7 * v dd_c for both cases, the signal is not to exceed: -0.3 v < clk32_in < v dd_c + 0.3 v power supply description the SIW3500 operates at 1.8 v core voltage for internal analog and digital circuits. the chip has internal analog and digital voltage regulators simplifying power supply requirements to the chip. the internal voltage regulators can be supplied directly from a battery or from other system voltage sources. optionally, the internal regulators can be by- passed if a 1.8 v regulated source is available on the system. note : both regulators can be bypassed if external regulation is desired. when bypassing the analog regulator, the vbatt_ana and vcc _out pins must be tied together and the external analog voltage (1.8 v) should be applied to the vbatt_ana pin. when bypassing the digita l regulator, the vbatt_dig pin should be left unconnected and the external digital voltage (1.8 v) shou ld be applied to vbb_out pin. the power for the i/os is taken from two separate sources (v dd_p and v dd_p_alt ). they can range from 1.62 to 3.63 volts to maintain compatibility with a wide range of peripheral devices. please check the pin list for the exact pins that are powered from the v dd_p and v dd_p_alt sources. function internal analog regulator internal digital regulator regulator input pin v batt_ana = 2.3 to 3.63 v v batt_dig = 2.3 to 3.63 v regulator output pin v cc_out = 1.8 v v dd_c = 1.8 v internal regulator used function analog core circuits digital core circuits circuit voltage supply pin v cc = 1.8 v v dd_c = 1.8 v internal regulator bypassed
preliminary 6 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds rf i/o description the SIW3500 employs single-ended rf input and output pins for reduced external components. in typical class 2 (0 dbm nominal) applications, no external matching components are necessary. on-chip memory the SIW3500 radio processor integrates both sram and rom. the rom is pre-programmed with bluetooth protocol stack software (hci software) and boot code that executes automatically upon reset. the boot code serves to control the boot sequence as well as to direct the execution to the appropriate memory for continued operation. configuration selection reference frequency selection the SIW3500 is designed to operate with multiple reference frequencies. during boot, specific frequency select i/o pins are sampled to determine the default reference frequency. the reference frequency setting will be set according to the following table: application software memory selection the SIW3500 can support application (protocol stack) software execution from internal rom or external flash memory. to run from internal rom, pins d[9] and d[10] must be connected together as shown in the application circuit section of this document (application circuit). to run from external flash memory, the flash must be connected as shown in the application circuit diagram and contain valid application code. if the external memory does not have valid program data, the device enters a download mode in which a valid program may be loaded into the external memory through a sequence of commands over the hci transport layer. freq_sel3 (mfp[3]) freq_sel2 (mfp[5]) freq_sel1 (mfp[4]) freq_sel0 (adc_in) frequency 000015.36 mhz 000119.2 mhz 001019.44 mhz 001119.68 mhz 010019.8 mhz 010126 mhz 011038.4 mhz 0111 do not program frequency (leave as ref/2 and set according to system parameters). 1 0 x x 32 mhz 110032 mhz 110112 mhz 111013 mhz 111114.4 mhz
preliminary 7 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds pin description the following table provides detailed listings of pin descriptions arranged by functional groupings. name pad type ball bump see note 1 description radio (power from vcc) rf_io analog a2 92 rf signal. input and output. tx_bias analog a4 89 internal transmitter driver bias. vtune analog a6 85 pin for reference pll loop filter, only used if reference fre- quency is not integer multiples of 4 mhz. chg_pump analog f1 10 pin for rf loop filter. xtal_n analog b7 82 system clock crystal negative i nput. if a reference clock is used, this pin should be left unconnected. xtal_p/clk analog a7 83 system clock crystal positive input or reference clock input. idac analog b1 1 power control to external power amplifier. this output pro- vides a variable current source that can be used to control the external power amp. leave unconnected if not used. adc_in analog j2 19 analog to digital converter input or freq_sel_(0). vrefn_cap analog c2 3 decoupling capacitor for internal a/d converter voltage refer- ence. vrefp_cap analog c1 2 decoupling capacitor for internal a/d converter voltage refer- ence. low power oscillator and reset (power from vdd_p_alt) clk32k_in analog l1 21 for crystal or external clock input (32.768 khz). clk32k_out analog k1 20 drive for crystal. reset_n cmos input g1 12 system level reset (active low). power control interface (power from vdd_p) pwr_reg_en cmos bi-directional g2 14 clock_req_out control line for external tcxo by default, or can be used as enable for an external voltage regulator. programmable active high or active low. aux_txd cmos bi-directional g9 58 auxiliary uart serial port output. multi-function (mfp) i/o (power from vdd_p) mfp [0] cmos bi-directional f3 15 multi-function i/o port. mfp [1] cmos bi-directional j1 17 multi-function i/o port. mfp [2] cmos bi-directional l6 35 multi-function i/o port. mfp [3] cmos bi-directional f1 0 59 multi-function i/o port. mfp [4] cmos bi-directional b9 76 multi-function i/o port. mfp [5] cmos bi-directional c8 77 multi-function i/o port. mfp [6] cmos bi-directional c7 80 multi-function i/o port. mfp [7] cmos bi-directional c6 81 multi-function i/o port. pcm interface (power from vdd_p_alt) pcm_in cmos bi-directional h3 28 pcm data output from SIW3500. pcm_out cmos bi-directional l2 23 pcm data input to SIW3500. pcm_clk cmos bi-directional k3 25 pcm synchronous data clock to the remote device. normally an output. input for slave mode. pcm_sync cmos bi-directional k2 22 pcm synchronization data strobe to the remote device. nor- mally an output. input for slave mode. table 1. SIW3500 radio processor pin list
preliminary 8 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds uart interface (power from vdd_p_alt) uart_rxd cmos input g3 24 uart receive data. uart_txd cmos output l4 29 uart transmit data. uart_cts cmos input h2 18 uart flow control clear to send. uart_rts cmos output h1 16 uart flow control ready to send. ext_wake cmos input c5 13 wake up signal from host. external memory interface (power from vdd_p) a[17] a[16] a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] cmos output e11 j11 l5 f11 b8 k6 l7 a10 h11 a11 b11 k9 k7 c10 k10 d10 l11 62 51 32 60 78 36 38 73 54 72 71 44 39 69 46 66 47 address lines. note : a[17] and a[16] can be used to support an optional external serial eeprom when using the internal rom in place of the external flash memory. d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] cmos bi-directional a9 c9 b10 e10 k5 g11 g10 h9 k4 j9 k8 j6 j5 f9 j4 h10 75 74 70 63 33 57 56 55 30 52 43 37 34 61 31 53 data lines. note : connect d[9] to d[10] to use internal rom. oe_n cmos output l10 45 output enable for external memory (active low). we_n/eeprom_wp cmos output a8 79 write enable for external memory (active low). fcs_n cmos output j10 50 chip select for external memory (active low). power and ground vbatt_ana power d3 6 positive supply to internal analog voltage regulator. vbatt_dig power l9 42 positive supply to internal digital voltage regulator. vcc_out power d1 5 regulated output from internal analog voltage regulator. vdd_p power d11 k11 65 48 positive supply for external memory interface and some digital i/os. vdd_c power c11 l8 68 41 positive supply for digital circuitr y or output of internal digital voltage. name pad type ball bump see note 1 description table 1. SIW3500 radio processor pin list (continued)
preliminary 9 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds vcc power a1 b6 c4 e1 e3 94 84 88 7 9 positive supply for rf and analog circuitry. vss_p gnd j8 e9 49 64 ground connections for vdd_p. vdd_p_alt power l3 26 positive supply for uart, codec, and other digital i/os. vss_p_alt ground j3 27 ground connection for vdd_p_alt. gnd gnd a3 a5 b2 b3 b4 b5 c3 d2 e2 f2 d9 j7 91 86 93 na 90 87 na 4 8 11 67 40 ground connections for rf and analog circuitry. 1. bump number information is provided as a reference to the known good die i/o configuration. name pad type ball bump see note 1 description table 1. SIW3500 radio processor pin list (continued)
preliminary 10 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds system specifications absolute maximum ratings recommended operating conditions esd rating electrical characteristics dc specification (t op =+25c, v dd_p =3.0v) ac characteristics (t op =+25c, v dd_p =3.0v, c load =15pf ) parameter description min max unit v dd_c digital circuit supply voltage -0.3 3.63 v v cc analog circuit supply voltage -0.3 3.63 v v dd_p, v dd_p_alt i/o supply voltage -0.3 3.63 v v batt_ana analog regulator supply voltage -0.3 3.63 v v batt_dig digital regulator supply voltage -0.3 3.63 v t st storage temperature -55 +125 c rf max maximum rf input level ? +5 dbm note : absolute maximum ratings indicate limits beyond which the useful life of the device may be impaired or damage may occur. parameter description min max unit t op operating temperature (industrial grade) -40 +85 c t eop extended operating temperature 1 -40 +105 c v batt_ana unregulated supply voltage into internal analog regulator 2.3 3.63 v v batt_dig unregulated supply voltage into in ternal digital regulator 2.3 3.63 v v cc regulated supply voltage directly into analog circuits 1.71 1.89 v v dd_c regulated supply voltage directly in to digital circuits 1.62 1.98 v v dd_p , v dd_p_alt digital interface i/o supply voltage 1.62 3.63 v 1. the extended operating temperature range applies to special order devices qualified for extended operating range. please contac t factory for details. symbol description rating esd esd protection - all pins 2000 v note: this device is a high performance rf integrated circuit with an esd rating of 2,000 volts (hbm conditions per mil-std-883, meth od 3015). handling and assembly of this device should only be done using appropriate esd controlled processes. symbol description min. typ max. unit v il input low voltage gnd-0.1 ? 0.3 . v dd_p v v ih input high voltage 0.7 . v dd_p ? v dd_p v v ol output low voltage gnd ? 0.2 . v dd_p v v oh output high voltage 0.8 . v dd_p ? v dd_p v i oh output high current ? 1 ? ma i ol output low current ? 1 ? ma i ili input leakage current ? 1 ? a symbol description typ max. unit t r rise time 5 11 ns t f fall time 5 8 ns
preliminary 11 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds current consumption (t op =+25c, v batt =3.0v using internal regulators) * note: continuous transmit and receive currents are measured in op erating modes where there is no activity in baseband digital c ircuits. digital regulator specification (t op = 25c) radio specification receiver specification 1 (v batt =3.3v, v cc =internal analog regulator output, t op = 25c) 1. measured into the chip with 50 ? source and no bandpass filter. 2. out-of-band blocking guaranteed by design. operating mode average max unit standby 40 80 a continuous transmit * 48 55 ma continuous receive * 54 60 ma parked slave, 1.28 sec. interval 90 ? a inquiry scan, 1.28 sec interval 440 ? a page scan, 1.28 sec. interval 560 ? a acl connection, sniff mode, 40 ms interval 1.3 ? ma acl data transfer 723 kbps tx, 57 kbps rx 42 ? ma sco connection, hv3 packets 22 ? ma parameter description min typ max unit output voltage (i out = 10 ma) 1.62 1.80 1.98 v line regulation (i out = 0 ma, v batt_dig = 2.3 v to 3.63 v) ?8.0 ?mv load regulation (i out = 3 ma to 80 ma) ?9.0 ?mv dropout voltage (i out = 10 ma) ? ? 250 mv output maximum current maximum supplied current while maintaining regulation ? ? 80 ma quiescent current off current ? 10 ? a ripple rejection f ripple = 400 hz ?40 ?db parameter description min typ max unit vco operating range frequency 2402 ? 2480 mhz pll lock time average tune time ? 60 100 s parameter description min typ max unit receiver sensitivity ber < 0.1% ? -85 -78 dbm maximum usable signal ber < 0.1% -10 0 ? dbm c/i co-channel (0.1% ber) co-channel selectivity ? +8.0 +10.0 db c/i 1 mhz (0.1% ber) adjacent channel selectivity ? -4.0 -3.0 db c/i 2 mhz (0.1% ber) 2nd adjacent channel selectivity ? -38.0 -35.0 db c/i 3 mhz (0.1% ber) 3rd adjacent channel selectivity ? -43.0 -40.0 db out-of-band blocking 2 fc/3 -23 ? ? dbm fc/2 -25 ? ? dbm 2 * fc/3 -45 ? ? dbm 30 mhz - 2000 mhz -10 ? ? dbm 2000 mhz - 2399 mhz -27 ? ? dbm 2498 mhz - 3000 mhz -27 ? ? dbm 3000 mhz - 12.75 ghz -10 ? ? dbm intermodulation max interferer level to maintain 0.1% ber, interference sig- nals at 3 and 6 mhz offset. -39 -36 ? dbm receiver spurious emission 30 mhz to 1 ghz ? ? -57 dbm 1 ghz to 12.75 ghz ? ? -47 dbm
preliminary 12 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds transmitter specification 1 (v batt =3.3v, v cc =internal analog regulator output, t op = 25c) 1. measured into the chip with 50 ? source and no bandpass filter. 2. modulation characteristics as measured per test trm/ca/07/c as defined in the bluetooth test specification. i ndustrial temperature performance 1 (v batt =2.3 ? 3.63v, v cc =internal analog regulator output, t op = -40 to +85c) parameter description min typ max unit output rf transmit power at maximum power output level -2 +2 +5 dbm modulation characteristics 2 ? f1 avg 140 155 175 khz ? f2 max ( for at least 99.9% of all ? f2 max ) 115 ? ? khz ? f1 avg / ? f2 avg 0.8 ? ? khz initial carrier frequency accuracy ? -75 ? +75 khz carrier frequency drift one slot packet -25 ? +25 khz two slot packet -40 ? +40 khz five slot packet -40 ? +40 khz max drift rate ? ? 20 khz/50 s 20 db occupied bandwidth test per bluetooth specification ? ? 1000 khz in-band spurious emission 2 mhz offset ? ? -40 dbm >3 mhz offset ? ? -60 dbm out-of-band spurious emission 30 mhz to 1 ghz, operating mode ? ? -55 dbm 30 mhz to 1 ghz, idle mode ? ? -57 dbm 1 ghz to 12.75 ghz, operating mode ? ? -50 dbm 1 ghz to 12.75 ghz, idle mode ? ? -47 dbm 1.8 ghz to 1.9 ghz ? ? -62 dbm 5.15 ghz to 5.3 ghz ? ? -47 dbm parameter description min typ max unit receiver sensitivity ber<0.1% ? -85 -75 dbm output rf transmit power at maximum power output level -4 +2 +6 dbm modulation characteristics 2 ? f1 avg 140 155 175 khz ? f2 max ( for at least 99.9% of all ? f2 max ) 115 ? ? khz ? f1 avg / ? f2 avg 0.8 ? ? khz initial carrier frequency accuracy ? -75 ? +75 khz carrier frequency drift one slot packet -25 ? +25 khz two slot packet -40 ? +40 khz five slot packet -40 ? +40 khz max drift rate ? ? 20 khz/50 s 20 db occupied bandwidth bluetooth specification ? ? 1000 khz in-band spurious emission 2 mhz offset ? ? -40 dbm >3 mhz offset ? ? -60 dbm out-of-band spurious emission 30 mhz to 1ghz, operating mode ? ? -55 dbm 30 mhz to 1ghz, idle mode ? ? -57 dbm 1 ghz to 12.75 ghz, operating mode ? -70 -50 dbm 1 ghz to 12.75 ghz, idle mode ? ? -47 dbm 1.8 ghz to 1.9 ghz ? ? -62 dbm 5.15 ghz to 5.3 ghz ? ? -47 dbm 1. measured into the chip with 50 ? impedance and no bandpass filter. industrial temperature performance guaranteed by design. 2. the modulation characteristic is measured as per test trm/ca/07/c defined in the bluetooth test specification.
preliminary 13 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds analog voltage supply requirements the SIW3500 processor is designed for use with its own internal low noise analog voltage regulator. this configuration is recommended for all applications. when necessary, the internal analog regulator can be bypassed. in situations where bypassing the internal analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve the rf performance characteristics. external reference requirements it is possible to provide a number of reference frequencies that are typical in most cellular phones directly into ball b7 (xtal_p/clk) of the device. refer to ?system reference clock? on page 5 for a list of supported reference frequencies. reference crystal requirements many reference frequencies are supported by the device. if a crystal is used as the reference frequency source, the typical required parameters are listed below: 1. for 32 mhz crystal. 2. if dc-coupled, the external reference signal voltage must stay within this range at all times. 3. the actual values for c o and c l are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibration capability. parameter description min max unit vcc analog supply voltage to al l vcc input pins 1.71 1.89 v minimum load current external regulator current 80 ? ma minimum ripple rejection at 400hz 40 ? db output noise integrated 10 hz to 80 khz noise ? 22 mv rms parameter description min max unit phase noise 100 hz offset ? -100 dbc/hz 1 khz offset ? -120 dbc/hz 10 khz offset ? -140 dbc/hz drive level ac amplitude 0.5 v cc v p-p dc level 1 1.if dc-coupled, the external reference signal voltage must stay within this range at all times. 0.3 v cc v parameter description min typ max unit drive level ? ? ? 0.3 mw esr effective serial resistance 1 ? ? 150 ? c o holder capacitance 2 ?35pf c l load capacitance 3 ?1218pf c m motional capacitance ? 6 ? ff
preliminary 14 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds application circuit internal rom version (for SIW3500gig vfbga package) host interface c4 18pf u1 c4 b1 c2 c1 d1 d3 e3 f1 g2 e11 j11 f11 l7 h9 h10 j4 j6 f9 l4 k8 j5 a10 a11 k6 f3 c11 h2 c5 k9 h11 g3 l9 j3 l3 j2 k1 l1 a8 g10 l6 k4 g11 k2 k3 k5 d11 l2 k7 c10 h3 h1 d10 k10 j9 b10 l11 c9 a9 b11 e10 b8 l10 k11 j10 l8 j1 l5 g1 b7 a7 b6 a6 e1 a4 a1 a2 j8 e9 a3 a5 b2 b3 b4 b5 c3 d9 d2 e2 f2 j7 f10 b9 c8 c7 c6 g9 vcc idac vrefp_cap vrefn_cap vcc_out vbatt_ana vcc chg_pump pwr_reg_en a[17]/eeprom_scl a[16]/eeprom_sda a[14] a[11] d[8]/pio[3] d[0] d[1] d[4]/pio[4] d[2] uart_txd d[5]/pio[5] d[3] a[10] a[8] a[12] mfp[0] vdd_c uart_cts ext_wake a[6] a[9] uart_rxd vbatt_dig vss_p_alt vdd_p_alt adc_in clk32k_out clk32k_in we_n/eeprom_wp d[9] mfp[2] d[7]/pio[7] d[10] pcm_sync pcm_clk d[11] vdd_p pcm_out a[5] a[4] pcm_in uart_rts a[2] a[3] d[6]/pio[6] d[13] a[1] d[14] d[15] a[7] d[12] a[13] oe_n vdd_p fcs_n vdd_c mpf[1] a[15] reset_n xtal_n xtal_p/clk vcc vtune vcc tx_bias vcc rf_io vss_p vss_p gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd mfp[3] mfp[4] mfp[5] mfp[6] mfp[7] aux_txd SIW3500gig (internal rom configuration) vbatt c5 18pf c3 1.5pf c10 0.1uf l1 2.2nh connect d[9] to d[10] to select internal rom mode. vdd_p antenna r1 47k c11 0.1uf c6 1uf c9 180pf y1 dsx221s 1 3 c8 22pf c7 8.2pf c2 1uf c1 0.1uf
preliminary 15 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds application circuit external flash version (for SIW3500gig vfbga package) c1 0.1uf u2 2m or 4m flash e1 d1 c1 a1 b1 d2 c2 a2 b5 a5 c5 d5 b6 a6 c6 d6 e6 b2 g1 a4 f1 a3 b3 c3 d3 b4 c4 d4 f6 e2 h2 e3 h3 h4 e4 h5 e5 f2 g2 f3 g3 f4 g5 f5 g6 g4 h1 h6 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 oe we ce ry/by# nc nc nc reset# nc nc byte# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 vcc gnd gnd c11 0.1uf c9 180pf r1 47k vbatt y1 xtl 32mhz 1 3 host interface SIW3500gig (external flash configuration) c8 22pf c7 8.2pf c12 0.1uf c6 1uf mfp[2] vdd_p note : for 4m flash, use mpf[2] for a17 pin c2 1uf antenna c10 0.1uf vdd_p c5 18pf u1 c4 b1 c2 c1 d1 d3 e3 f1 g2 e11 j11 f11 l7 h9 h10 j4 j6 f9 l4 k8 j5 a10 a11 k6 f3 c11 h2 c5 k9 h11 g3 l9 j3 l3 j2 k1 l1 a8 g10 l6 k4 g11 k2 k3 k5 d11 l2 k7 c10 h3 h1 d10 k10 j9 b10 l11 c9 a9 b11 e10 b8 l10 k11 j10 l8 j1 l5 g1 b7 a7 b6 a6 e1 a4 a1 a2 j8 e9 a3 a5 b2 b3 b4 b5 c3 d9 d2 e2 f2 j7 f10 b9 c8 c7 c6 g9 vcc idac vrefp_cap vrefn_cap vcc_out vbatt_ana vcc chg_pump pwr_reg_en a[17]/eeprom_scl a[16]/eeprom_sda a[14] a[11] d[8]/pio[3] d[0] d[1] d[4]/pio[4] d[2] uart_txd d[5]/pio[5] d[3] a[10] a[8] a[12] mfp[0] vdd_c uart_cts ext_wake a[6] a[9] uart_rxd vbatt_dig vss_p_alt vdd_p_alt adc_in clk32k_out clk32k_in we_n/eeprom_wp d[9] mfp[2] d[7]/pio[7] d[10] pcm_sync pcm_clk d[11] vdd_p pcm_out a[5] a[4] pcm_in uart_rts a[2] a[3] d[6]/pio[6] d[13] a[1] d[14] d[15] a[7] d[12] a[13] oe_n vdd_p fcs_n vdd_c mpf[1] a[15] reset_n xtal_n xtal_p/clk vcc vtune vcc tx_bias vcc rf_io vss_p vss_p gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd mfp[3] mfp[4] mfp[5] mfp[6] mfp[7] aux_txd c3 1.5pf c4 18pf l1 2.2nh
preliminary 16 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds vfbga i/o configuration (top view) 1234567891011 a b c d e f g h j k l vcc rf_io gnd vref p_cap gnd gnd gnd vref n_cap vcc_ out gnd vcc gnd idac gnd vcc vtune ext_ wake gnd tx_ bias vcc vbatt_ ana mfp[7] gnd a[9] d[4] d[9] d[7] mfp[5] d[3] a[11] d[11] a[13] xtal_ p/clk mfp[3] gnd vdd_p d[2] uart_ cts mfp[1] clk_ 32k_ out chg_ pump clk_ 32k_ in gnd a[1] d[13] a[3] a[15] fcs_n vdd_c a[8] pcm_ clk vcc pcm_ out aux_ xtd mfp[6] uart_ rts mfp[0] reset_ n mfp[2] a[17] a[12] a[16] oe_n gnd a[14] mfp[4] d[12] d[10] vdd_p we_n xtal_n a[5] a[4] d[14] a[7] uart_ txd uart_ rxd vdd_ p_alt pcm_in pwr_ reg_ en pcm_ sync d[6] adc_in a[6] vss_p d[15] vdd_c d[8] d[1] d[0] d[5] a[2] vbatt_ dig a[10] vss_p_ alt 1234567891011 vss_p
preliminary 17 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds known good die i/o configuration (bottom view, bumped side) 1. idac 2. vrefp_cap 3. vrefn_cap 4. gnd 5. vcc_out 6. vbatt_ana 7. vcc 8. gnd 9. vcc 10. chg_pump 11. gnd 12. reset_n 13. ext_wake 14. pwr_reg_en 15. mfp[0] 16. uart_rts 17. mfp[1] 18. uart_cts 19. adc_in 20. clk32k_out 21. clk32k_in 22. pcm_sync 23. pcm_out 24. uart_rxd 25. pcm_clk 26. vdd_p_alt 27. vss_p_alt 28. pcm_in 29. uart_txd 30. d[7] 31. d[1] 32. a[15] 33. d[11] 34. d[3] 35. mfp[2] 36. a[12] 37. d[4] 38. a[11] 39. a[5] 40. gnd 41. vdd_c 42. vbatt_dig 43. d[5] 44. a[6] 45. oe_n 46. a[3] 47. a[1] 48. vdd_p 49. vss_p 50. fcs_n 51. a[16] 52. d[6] 53. d[0] 54. a[9] 55. d[8] 56. d[9] 57. d[10] 58. aux_txd 59. mfp[3] 60. a[14] 61. d[2] 62. a[17] 63. d[12] 64. vss_p 65. vdd_p 66. a[2] 67. gnd 68. vdd_c 69. a[4] 70. d[13] 71. a[7] 72. a[8] 73. a[10] 74. d[14] 75. d[15] 76. mfp[4] 77. mfp[5] 78. a[13] 79. we_n 80. mfp[6] 81. mfp[7] 82. xtal_n 83. xtal_p/clk 84. vcc 85. vtune 86. gnd 87. gnd 88. vcc 89. tx_bias 90. gnd 91. gnd 92. rf_io 93. gnd 94. vcc y x (0,0) 3.70 mm 0.05mm 3.70 mm 0.05mm 1 3 5 7 9 11 13 15 17 19 21 22 24 25 26 28 30 32 34 36 38 40 42 44 46 45 23 27 29 31 33 35 37 39 41 43 91 89 87 85 83 81 79 77 75 73 92 94 80 78 74 76 72 71 70 82 84 86 88 90 93 2 4 6 8 10 12 14 16 18 20 68 64 62 60 58 56 54 52 50 48 66 53 51 47 49 55 67 63 61 59 57 65 69
preliminary 18 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds SIW3500 radio processor bump description and location die bump no. net name ball no. see note 1 x (m) see note 2 y (m) see note 2 1idac b1 -1675 1316 2 vrefp_cap c2 -1675 1066 3 vrefn_cap c1 -1425 1061.5 4gnd d2 -1675 760 5 vcc_out d1 -1458.3 607 6 vbatt_ana d3 -1675 454 7vcc e1 -1241.75 392 8gnd e2 -1675 148 9vcc e3 -1458.3 7.2 10 chg_pump f1 -1675 -117.5 11 gnd f2 -1458.3 -367 12 reset_n g1 -1675 -492 13 ext_wake c5 -1458.3 -617 14 pwr_reg_en g2 -1675 -742 15 mfp[0] f3 -1458.3 -867 16 uart_rts h1 -1675 -992 17 mfp[1] j1 -1241.75 -992 18 uart_cts h2 -1675 -1242 19 adc_in j2 -1458.3 -1117 20 clk32k_out k1 -1675 -1492 21 clk32k_in l1 -1458.3 -1367 22 pcm_sync k2 -1064.5 -1241.9 23 pcm_out l2 -1189.5 -1458.45 24 uart_rxd g3 -1314.5 -1675 25 pcm_clk k3 -814.5 -1241.9 26 vdd_p_alt l3 -1064.5 -1675 27 vss_p_alt j3 -939.5 -1458.45 28 pcm_in h3 -814.5 -1675 29 uart_txd l4 -689.5 -1458.45 30 d[7] k4 -537 -1675 31 d[1] j4 -412 -1458.45 32 a[15] l5 -287 -1675 33 d[11] k5 -162 -1458.45 34 d[3] j5 -37 -1675 35 mfp[2] l6 88 -1458.45 36 a[12] k6 213 -1675 37 d[4] j6 338 -1458.45 38 a[11] l7 463 -1675 39 a[5] k7 588 -1458.45
preliminary 19 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds 40 gnd j7 713 -1675 41 vdd_c l8 838 -1458.45 42 vbatt_dig l9 990.5 -1675 43 d[5] k8 1115.5 -1458.45 44 a[6] k9 1240.5 -1675 45 oe_n l10 990.5 -1241.9 46 a[3] k10 1490.5 -1675 47 a[1] l11 1241.85 -1123 48 vdd_p k11 1675 -1373 49 vss_p j8 1458.4 -1248 50 fcs_n j10 1675 -1123 51 a[16] j11 1241.85 -873 52 d[6] j9 1675 -873 53 d[0] h10 1241.85 -623 54 a[9] h11 1675 -623 55 d[8] h9 1458.4 -498 56 d[9] g10 1675 -373 57 d[10] g11 1458.4 -248 58 aux_txd g9 1675 -123 59 mfp[3] f10 1458.4 2 60 a[14] f11 1675 127 61 d[2] f9 1458.4 252 62 a[17] e11 1675 377 63 d[12] e10 1458.4 502 64 vss_p e9 1675 627 65 vdd_p d11 1458.4 752 66 a[2] d10 1675 877 67 gnd d9 1458.4 1002 68 vdd_c c11 1675 1127 69 a[4] c10 1241.85 877 70 d[13] b10 1675 1377 71 a[7] b11 1458.4 1252 72 a[8] a11 1207.5 1241.9 73 a[10] a10 1457.5 1675 74 d[14] c9 1082.5 1458.45 75 d[15] a9 1207.5 1675 76 mfp[4] b9 957.5 1241.9 77 mfp[5] c8 957.5 1675 78 a[13] b8 832.5 1458.45 79 we_n a8 707.5 1675 die bump no. net name ball no. see note 1 x (m) see note 2 y (m) see note 2
preliminary 20 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds 80 mfp[6] c7 582.5 1458.45 81 mfp[7] c6 457.5 1675 82 xtal_n b7 332.5 1446.95 83 xtal_p/clk a7 105 1675 84 vcc b6 -20 1458.45 85 vtune a6 -145 1675 86 gnd a5 -180.5 1241.9 87 gnd b5 -395 1675 88 vcc c4 -644.5 1241.9 89 tx_bias a4 -645 1675 90 gnd b4 -770 1458.45 91 gnd a3 -895 1675 92 rf_io a2 -1145 1675 93 gnd b2 -1399.15 1458.5 94 vcc a1 -1526 1675 1 ball number information is provided as a re ference to the 6-by-6-mm bga packaged device. 2 x, y bump locations are referenced to the center of the die. die bump no. net name ball no. see note 1 x (m) see note 2 y (m) see note 2
preliminary 21 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds packaging and pr oduct marking package drawing green package, 96-pin, 6 mm x6 mm, vfbga drawing and dimensions symbol min max notes: a0.81.0 1. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. a1 0.2 0.3 a2 0.22 ref 2. datum z is defined by the spherical crowns of the solder balls. a3 0.45 ref b0.250.35 3. parallelism measurement shall exclude any effect of mark on top surface of package. d6 bsc e6 bsc 4. all dimensions are in millimeters. e 0.5 bsc d1 5 bsc 5. vfbga green package solder ball material: 95.5% sn, 4% ag, 0.5% cu. e1 5 bsc b
preliminary 22 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds packaging and product marking green package, known good die, drawing and dimensions symbol min (m) max (m) notes: a 375 415 1. dimension b is measured at the solder bump diameter at the bump base, parallel to datum plane z. a1 100 m 15 m 2. datum z is defined by the spherical crowns of the solder bumps. b 130 nom 3. all dimensions are in micrometers except as noted. d 3.70 mm 0.05mm 4. kgd solder bump material: 97.7% sn, 2.3% 0.5% ag e 3.70 mm 0.05mm 5. pitch: minimum bump pitch: some bumps exhibit greater than 250 m pitch. bump pitch 250 ? y x (0,0) 1 3 5 7 9 11 13 15 17 19 21 22 24 25 26 28 30 32 34 36 38 40 42 44 46 45 23 27 29 31 33 35 37 39 41 43 91 89 87 85 83 81 79 77 75 73 92 94 80 78 74 76 72 71 70 82 84 86 88 90 93 2 4 6 8 10 12 14 16 18 20 68 64 62 60 58 56 54 52 50 48 66 53 51 47 49 55 67 63 61 59 57 65 69 bottom view 3.70 mm 0.05mm 0.015 backside finish is si side view 3.70 mm 0.05mm b
preliminary 23 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds product marking 6 x 6 mm, 96-pin, vfbga 3.7 x 3.7 mm, known good die SIW3500gig1 siw pin 1 corner arm yyww lllll 4 digit date code trace code pin 1 bar notes : 1) assembly house to fill in yyww with the date code: yy = year ww = week 2) trace code determined at assembly time. 3) the laser marking depth is 1 - 2 m typical, 3 m maximum. 4) the laser marking shall be visible at 10x magnification. marking technique to be used: ink marking laser marking 3500 dif1 yyww trace code pin 1 indicator
preliminary 24 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds carriers tape and reel SIW3500gig, 6 x 6 mm 96-pin, vfbga, tape details carrier tape basic dimensions are based on eia481. the pocket is designed to hold the part for shipping and loading onto smt manufacturing equipment, while protecting the body and the solder terminals from damaging stresses. the individual pocket design can vary from vendor to vendor, but width and pitch will be consistent. carrier tape is wound or placed onto a shipping reel either 330 mm (13 inches) in diameter or 178 mm (7 inches) in diameter. the center hub design is large enough to ensure the radius formed by the carrier tape around it does not put unnecessary stress on the parts. prior to shipping, moisture sensitive parts (msl-3) are baked and placed into the pockets of the carrier tape. a cover tape is sealed over the top of the entire length of the carrier tape. the reel is sealed in a moisture barrier, esd bag, which is placed in a cardboard shipping box. it is important to note that unused moisture sensitive parts need to be resealed in the moisture barrier bag. if the reels exceed the exposure limit and need to be rebaked, carrier tape and shipping reels are not bakeable at 125c. if baking is required, devices may be baked according to section 4, table 4-1, column 8 of joint industry standard ipc/jedec j-std-033a. rfmd part number reel diameter inch (mm) hub diameter inch (mm) width (mm) pocket pitch (mm) feed units per reel SIW3500gig1-tr13 13 (330) 4 (102) 16 12 single 2500 15 inch leader w p 2.0 .1 4.0 .1 1.75 .10 f ko bo ao 0.30 .05 pin 1 location 15 inch trailer top view part number trace code yyw w arm part number trace code yyw w arm part number trace code yyw w arm part number trace code yyw w arm 0.25 .10 ?1.5.1 ao = 6.30 .10 bo = 6.30 .10 f = 7.50 .10 ko = 1.50 .10 p = 12.00 .10 w = 16.00 .30 notes: 1. all dimensions are in millimeters (mm). 2. unless otherwise specified, all dimension tolderances per eia-481. sprocket holes toward rear of reel direction of feed . .
preliminary 25 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds SIW3500dif, known good die, tape details carrier tape basic dimensions are based on eia481. the pocket is designed to hold the part for shipping and loading onto smt manufacturing equipment, while protecting the body and the solder terminals from damaging stresses. the individual pocket design can vary from vendor to vendor, but width and pitch will be consistent. carrier tape is wound or placed onto a shipping reel 330 mm (13 inches) in diameter. the center hub design is large enough to ensure the radius formed by the carrier tape around it does not put unnecessary stress on the parts. prior to shipping, parts are placed into the pockets of the carrier tape. a cover tape is sealed over the top of the entire length of the carrier tape. the reel is sealed in a moisture barrier esd bag with a dry n2 backfill, which is placed in a cardboard shipping box. it is important to note that unused parts need to be resealed in the moisture barrier bag. if baking is required, devices may be baked according to section 4, table 4-1, column 8 of joint industry standard ipc/jedec j-std-033a. notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber not to exceed 1 mm in 100 mm. 3. material: black advantek polystyrene. 4. ao and bo measured on a plane 0.3 mm above the bottom of the pocket. 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7. all dimensions in millimeters. 8. tolerances (except as noted): decimal 0.1. rfmd part number reel diameter inch (mm) hub diameter inch (mm) width (mm) pocket pitch (mm) feed units per reel SIW3500dif1-tr13 13 (330) 4 (102) ? ? single 2500 a b b 1.75 a 1.50 +0.1 -0.0 8.00 4.50 2.00 0.05 5.50 0.05 12.00 0.03 see note 6 see note 6 see note 1 4.00 ao section b-b bo 0.21 0.03 r0.30 (typ.) ko section a-a 3.00 ao= 4.00 mm bo= 4.00 mm ko= 0.70 mm direction of feed
preliminary 26 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds SIW3500dif, known good die, reel details peel test peel angle cover tape leader trailer peel speed 10?50 grams 165-180 o rs standard (anti-static) 500 mm (minimum 400 mm) 250 mm (minimum 160 mm) 300 mm/minute
preliminary 27 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds ordering information part number operational temperature range 1 package solder ball/bump composition ordering quantity SIW3500gig1 industrial 6x6, 96-pin vfbga, green package 95.5% sn, 4% ag, 0.5% cu 25 pcs on cut tape SIW3500gig1sb industrial 6x6, 96-pin vfbga, green package 95.5% sn, 4% ag, 0.5% cu 5 pcs on cut tape SIW3500gig1sr industrial 6x6, 96-pin vfbga, green package 95.5% sn, 4% ag, 0.5% cu 100 pcs on short reel SIW3500gig1-t13 industrial 6x6, 96-pin vfbga, green package 95.5% sn, 4% ag, 0.5% cu 2500 on 13? reel SIW3500dif1 industrial known good die 2 , green 97.7% sn, 2.3% 0.5% ag 25 pcs on cut tape SIW3500dif1sb industrial known good die 2 , green 97.7% sn, 2.3% 0.5% ag 5 pcs on cut tape SIW3500dif1sr industrial known good die 2 , green 97.7% sn, 2.3% 0.5% ag 100 pcs on short reel SIW3500dif1-t13 industrial known good die 2 , green 97.7% sn, 2.3% 0.5% ag 2,500 on 13? reel 1. industrial temperature range: -40c to +85c. 2. for additional technical details about known good die, please refer to rf micro devices document 60 0071 SIW3500dif bumped d ie manufacturing notes.
preliminary 28 of 28 SIW3500 60 0066 r00irf SIW3500 radio processor ds the information in this publication is believed to be accurate and reliable. however, no responsibility is assumed by rf micro devices for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. no license is granted by implication or otherwise under any patent or patent rights of rf micro devices, inc. rf micro devices reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. rf micro devices?, rfmd?, optimum technology matching?, enabling wireless connectivity?, ultimateblue?, and the siw product name prefix are trademarks of rfmd, llc. bluetooth is a trademark owned by bluetooth sig, inc., u.s.a. and licensed for use by rf micro devices, inc. manufactured under license from arm limited. arm, arm7tdmi and the arm logo are the registered trademarks of arm limited in the eu and other countries. all other trade names, trademarks and registered trademarks are the property of their respective owners.

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